TSMC’s new packaging technology will bring down chip cost and improve performance | Infinium-tech
According to sources familiar with the matter, TSMC is working on a cutting-edge technology called CoPoS for chip packaging. CoPoS stands for chip-on-panel-on-structure, and it uses a glass material that acts as a temporary carrier, and it also goes into the final substrate with a three-layer sandwich structure.
Reportedly, TSMC will begin mass production of chips using CoPoS by the end of 2028. The new technology will reportedly reduce manufacturing costs and improve performance.
In fact, Nvidia’s Feynman AI chipset will be the first chipset to use CoPoS. This is because the next generation of packaging will be used primarily for AI and high-performance computing chips.
If CoPoS proves to be a game-changer, it would cement TSMC’s leading market position as a chip maker, forcing rival companies to introduce alternative technologies.
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